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CXD2931R-9/GA-9
1 chip GPS LSI
Description The CXD2931R-9/GA-9 is a dedicated LSI for the GPS (Global Positioning System) satellite-based position measurement system. This LSI contains a 32-bit RISC CPU, 2M-bit MASK ROM, RAM, UART, timer, and others. This LSI, used together with the RF LSI (CXA1951AQ), enables the configuration of a 2-chip system capable of measuring its position anywhere on the globe. Features * 16-channel GPS receiver capable of simultaneously receiving 16 satellites * Supports differential GPS -- Comforms to RTCM SC-104 Ver. 2.1 -- Supports DARC * All-in-view measurement * 2-satellite measurement * Timer supporting GPS time * High performance 32-bit RISC CPU * 256K-byte program ROM * 36K-byte RAM * 3-channel UART -- Baud rate generator -- Supports 1.2K, 2.4K, 4.8K, 9.6K, 19.2K and 38.4K baud -- Supports 1/2/4-byte buffer mode * 23-bit general-purpose I/O port capable of defining input/output independently for each bit * 8-bit successive approximation system A/D converter Structure Silicon gate CMOS IC CXD2931R-9 144 pin LQFP (Plastic) CXD2931GA-9 144 pin LFLGA (Plastic)
Absolute Maximum Ratings * Supply voltage VDD VSS - 0.5 to 4.6 * Input voltage VI VSS - 0.5 to VDD + 0.5 * Output voltage VO VSS - 0.5 to VDD + 0.5 * Operating temperature Topr -40 to +85 * Storage temperature Tstg -50 to +150 Recommended Operating Conditions 3.0 to 3.6 * Supply voltage VDD * Operating temperature Topr -40 to +85 Input/Output Pin Capacitance * Input capacitance CIN 9 (Max.) * Output capacitance COUT 11 (Max.) * I/O capacitance CI/O 11 (Max.)
V V V C C
V C
pF pF pF
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E01Z12A22-PS
CXD2931R-9/GA-9
Performance * 16-channel GPS receiver * High performance 32-bit RISC CPU * Receiver frequency: 1575.42MHz (L1 band, CA code) * Reception sensitivity Tracking sensitivity: -145dBm (typ.) when using the antenna of 25dBi, NF = 2dB and the RF amplifier with the 25dB gain Reference data using the Sony's reference board. This value is not guaranteed, depending on the conditions. * Time to First Fix (time until initial measurement after power-on) Cold Start (without both ephemeris and almanac): 27 to 58s Warm Start (without ephemeris with almanac): 23 to 45s Hot Start (with both ephemeris and almanac): 6 to 17s Reference data with elevation angle of 5 or more and no interception environment on Nov., 2001. Positioning time with 90% possibility. These values are not guaranteed, depending on the conditions. * Positioning accuracy 2DRMS: approx. 12m Reference data with elevation angle of 5 or more and no interception environment. This value is not guaranteed, depending on the conditions. * Measurement data update time 1s * Interfece format NMEA0183 (4800bps) * Communication method Start-stop synchronization * All-in-view
LNA 1575.42MHz
CXA1951AQ RF Converter 18.414MHz TCXO IF 1.023MHz TXD CXD2931R-9 16ch GPS Processor RXD
GPS receiver system block diagram using the CXD2931R-9 -2-
CXD2931R-9/GA-9
Block Diagram
DCS0 to DCS5/PORT (16:21)
DADR (0:15)
PORT (0:15)
IADR (1:18)
IB (0:15)
DB (0:7)
ICS0, 1
XCS0
DWR
DRD
IWR
IRD
TEST0, 1 RUN BIU ICST0, 1 XROMW HOLD NMI PMI IODBK HOLDA SINT/PORT (22) 32-bit RISC CLKO CLKOUT TCXOS CLKS CLKI
256K-byte ROM
EXRS PWRST
36K-byte SRAM VDD x 10 TXD0 to TXD2 RXD0 to RXD2 VSS x 10 UART (Baud Rate Generator) x 3
TIMER x 3 AVD 16ch GPS DSP 8-bit ADC AVS VRT VRB
CCKI
XTCXO
OTCXO
CCKO
TCXO
-3-
AVIN
IF0O
IF0
CXD2931R-9/GA-9
Pin Configuration (CXD2931R-9)
DADR15
DADR14
DADR13
DADR12
DADR11
DADR10
DADR9
DADR8
DADR7
DADR6
DADR5
DADR4
DADR3
DADR2
DADR1
DADR0
XCS0
DWR
DRD
IB15
IB14
IB13
IB12
IB11
IB10
DB5
DB4
DB3
DB2
DB1
DB0
VDD
VDD
VSS
VSS
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 DB6 109 DB7 110 SINT/PORT22 111 DCS0/PORT21 112 VDD 113 DCS1/PORT20 114 DCS2/PORT19 115 DCS3/PORT18 116 DCS4/PORT17 117 DCS5/PORT16 118 PORT15 119 PORT14 120 VSS 121 PORT13 122 PORT12 123 PORT11 124 PORT10 125 PORT9 126 PORT8 127 PORT7 128 VDD 129 PORT6 130 PORT5 131 PORT4 132 PORT3 133 PORT2 134 PORT1 135 PORT0 136 VSS 137 TXD2 138 RXD2 139 TXD1 140 RXD1 141 TXD0 142 RXD0 143 VDD 144 72 IB8 71 IB7 70 VSS 69 IB6 68 IB5 67 IB4 66 IB3 65 IB2 64 IB1 63 VDD 62 IB0 61 IADR18 60 IADR17 59 IADR16 58 IADR15 57 IADR14 56 IADR13 55 VSS 54 IADR12 53 IADR11 52 IADR10 51 IADR9 50 IADR8 49 IADR7 48 IADR6 47 VDD 46 IADR5 45 IADR4 44 IADR3 43 IADR2 42 IADR1 41 XROMW 40 ICS1 39 VSS 38 ICS0 37 IRD
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
XTCXO
TCXOS
HOLDA
IODBK
PWRST
CLKOUT
HOLD
CCKI
OTCXO
CCKO
CLKS
VRT
VRB
NMI
PMI
TCXO
ICST0
ICST1
TEST0
TEST1
EXRS
-4-
CLKO
AVIN
IF0O
CLKI
RUN
AVD
IWR
VDD
VSS
VSS
VDD
VSS
AVS
VDD
IF0
IB9
CXD2931R-9/GA-9
Pin Configuration (CXD2931GA-9)
70 VSS 75 VDD 78 IB13 81 DRD 83 XCS0 86 VSS 87
67 IB4 71 IB7 74 IB10 77 IB12 79 IB14 82 DWR 85
64 IB1 68 IB5 72 IB8 73 IB9 76 IB11 80 IB15 84
62 IB0 66 IB3 69 IB6
59
58
55 VSS 56
54
51
50 IADR8 46 IADR5 44 IADR3
47 VDD 43
45 IADR4 41
42 IADR1 38 ICS0 36 IWR 33 CLKOUT 29 VSS 25 HOLDA 21 VDD 16 ICST0 12 TEST1 8
39 VSS 35 RUN 32
34 VDD 31 CLKO 28
R
IADR16 IADR15 63 VDD 65 IB2 60
IADR12 IADR9 53 49
P
IADR17 IADR13 IADR11 IADR7 61 57 52 48
IADR2 XROMW 40 ICS1 37 IRD
N
IADR18 IADR14 IADR10 IADR6
CLKS PWRST 30 CLKI 27 EXRS 24 PMI 20 TCXOS 17 ICST1 13 CCKI 10 26 IODBK 23 NMI 22 HOLD 19 IF0O 18 IF0 15 VSS 14 F G H J K L M
DADR2 DADR1 DADR0 90 89 88
DADR5 DADR4 DADR3 91 92 93
DADR6 DADR7 DADR8 94 96 97
DADR9 DADR10 DADR11 95 VDD 98 DADR12 100 DADR14 103 DB1 106 DB3 99 101
XTCXO OTCXO CCKO 4 VRB 1 AVD 109 DB6 113 VDD 117 112 116 120 124 129 VDD 128 133 PORT3 132 137 VSS 135 141 RXD1 138 TXD2 134 144 VDD 140 TXD1 136 7 TCXO 5 AVS 2 AVIN 143 RXD0 139 RXD2 11 TEST0 9 VDD 6 VSS 3 VRT 142 TXD0 A B C D E
DADR13 DADR15 102 DB0 104 VSS 107 DB4 111 105 DB2 108 DB5 110 DB7 114
DCS0/ DCS3/ PORT14 PORT11 PORT21 PORT18
115
118
121 VSS 123
125
DCS2/ DCS5/ PORT19 PORT16
PORT10 PORT7 PORT4 PORT1 126 127 130 131
119
122
SINT/ DCS1/ DCS4/ PORT15 PORT13 PORT12 PORT9 PORT8 PORT6 PORT5 PORT2 PORT0 PORT22 PORT20 PORT17
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
-5-
CXD2931R-9/GA-9
Pin Configuration Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 Symbol AVD AVIN VRT VRB AVS Vss TCXO XTCXO VDD OTCXO TEST0 TEST1 CCKI CCKO Vss ICST0 ICST1 IF0 IF0O TCXOS VDD HOLD NMI PMI HOLDA IODBK EXRS PWRST Vss CLKI CLKO CLKS CLKOUT VDD RUN IWR IRD I/O -- I I I -- -- I O -- O I I I O -- I I I O I -- I I I O O I I -- I O I O -- O O O A/D converter power supply. Analog input. Reference input. A/D converter GND. GND TCXO binary conversion circuit/crystal oscillator. Power supply. TCXO clock output. Test. (Low level fixed) Timer oscillation. (32.768kHz 100ppm) GND Test. (Low level fixed) IF signal binary conversion circuit. TCXO select. (Low: TCXO/2, High: TCXO through) Power supply. Hold input signal. (High: Hold) Non maskable interrupt. Program maskable interrupt. Hold acknowledge signal. Break signal for debugging. Reset input signal. Connect to main power supply. Leave open during backup. GND CPU clock oscillation circuit. CPU clock select signal. (Low: TCXO, High: CLKI) CPU clock output. Power supply. Signal indicating CPU operating status. Write signal for external expansion memory. Read signal for external expansion memory. -6- Description
CXD2931R-9/GA-9
Pin No. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 Vss
Symbol ICS0 ICS1 XROMW IADR1 IADR2 IADR3 IADR4 IADR5 VDD IADR6 IADR7 IADR8 IADR9 IADR10 IADR11 IADR12 Vss IADR13 IADR14 IADR15 IADR16 IADR17 IADR18 IB0 VDD IB1 IB2 IB3 IB4 IB5 IB6 Vss IB7 IB8 IB9 IB10
I/O O -- O I I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O -7- GND (MSB) GND Power supply.
Description Chip select 0 for external expansion memory. GND Chip select 1 for external expansion memory. Wait signal for external expansion memory. (High: Wait) (LSB) Address signal for external expansion memory.
Address signal for external expansion memory.
Address signal for external expansion memory.
(LSB) Data bus I/O for external expansion memory. Power supply.
Data bus I/O for external expansion memory.
Data bus I/O for external expansion memory.
CXD2931R-9/GA-9
Pin No. 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 VDD
Symbol
I/O -- I/O I/O I/O I/O I/O O O O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O (MSB) (MSB) Power supply. (MSB) Power supply.
Description
IB11 IB12 IB13 IB14 IB15 DRD DWR XCS0 DADR0 DADR1 Vss DADR2 DADR3 DADR4 DADR5 DADR6 DADR7 DADR8 DADR9 VDD DADR10 DADR11 DADR12 DADR13 DADR14 DADR15 DB0 DB1 Vss DB2 DB3 DB4 DB5 DB6 DB7
Data bus I/O for external expansion memory.
Read signal for external expansion data memory. Write signal for external expansion data memory. Chip select signal for external expansion data memory. (LSB) Address signal for external expansion data memory. GND
Address signal for external expansion data memory.
Address signal for external expansion data memory.
(LSB) Data bus I/O for external expansion data memory. GND
Data bus I/O for external expansion data memory.
-8-
CXD2931R-9/GA-9
Pin No. 111
Symbol SINT/PORT22
I/O I/O
Description External interrupt input signal/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. Chip select for external expansion data memory/general-purpose I/O port. This pin can be used as a general-purpose I/O port according to the internal registers. Power supply.
112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144
DCS0/PORT21 VDD DCS1/PORT20 DCS2/PORT19 DCS3/PORT18 DCS4/PORT17 DCS5/PORT16 PORT15 PORT14 Vss PORT13 PORT12 PORT11 PORT10 PORT9 PORT8 PORT7 VDD PORT6 PORT5 PORT4 PORT3 PORT2 PORT1 PORT0 Vss TXD2 RXD2 TXD1 RXD1 TXD0 RXD0 VDD
I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- I/O I/O I/O I/O I/O I/O I/O -- O I O I O I --
Chip select for external expansion data memory/general-purpose I/O port. These pins can be used as a general-purpose I/O port according to the internal registers.
General-purpose I/O port. GND
General-purpose I/O port.
Power supply.
General-purpose I/O port.
GND UART transmission data output. (channel 2) UART reception data input. (channel 2) UART transmission data output. (channel 1) UART reception data input. (channel 1) UART transmission data output. (channel 0) UART reception data input. (channel 0) Power supply.
-9-
CXD2931R-9/GA-9
A/D Converter Characteristics Item Resolution Differential linearity error (DLE) Integral linearity error (ILE) Sampling time Conversion time Current consumption Pin
(0 < VRB < VIN < VRT < AVD = 3.0 to 3.6V, Topr = -40 to +85C) Condition Min. -0.5 -2.5 648 864 2.0 Typ. Max. 8 AVD = 3.0V f = 18.414MHz AVD = 3.0V +0.5 +2.5 Unit Bit LSB LSB ns ns mA
Electrical Characteristics DC Characteristics Item Input voltage (1) (CMOS level) Input voltage (2) (5V interface) Output voltage (1) Output voltage (2) Output voltage (3) High level Low level High level Low level High level Low level High level Low level High level Low level Symbol VIH (1) VIL (1) VIH (2) VIL (2) VOH (1) VOL (1) VOH (2) VOL (2) VOH (3) VOL (3) IOH = -4.0mA IOL = 4.0mA IOH = -2.0mA IOL = 4.0mA IOH = -2.0mA IOL = 8.0mA VDD = 3.0V VDD = 1.8V f = 18.414MHz 20 4 55 VDD - 0.8 0.4 70 50 VDD - 0.8 0.4 VDD - 0.4 0.4 0.7 x VDD Condition (VDD = 3.0 to 3.6V, Topr = -40 to +85C) Min. 0.7 x VDD Typ. Max. VDD 0.2 x VDD 5.5 0.2 x VDD Unit Applicable Pins V V V V V V V V V V A mA -- -- 5 4 3 2 1
Current consumption in standby mode ISTB (Using external timer, +85C) Supply current IDD
Applicable pins 1 Pins 11, 12, 16, 17, 20, 28, 32, 41 2 Pins 22 to 24, 27, 62, 64 to 69, 71 to 74, 76 to 80, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122, 128, 130 to 136, 139, 141, 143 3 Pins 10, 25, 26, 33, 35 4 Pins 38, 40, 82, 83, 138, 140, 142 5 Pins 36, 37, 42 to 46, 48 to 54, 56 to 62, 64 to 69, 71 to 74, 76 to 81, 84, 85, 87 to 94, 96 to 103, 105 to 112, 114 to 120, 122 to 128, 130 to 136
- 10 -
CXD2931R-9/GA-9
Battery Backup Mode The battery backup mode is activated when the power for the GPS receiver is turned off and power-on reset goes to low level. The timer clock continues to operate even when power-on reset goes low, but all other clock are fixed high and the LSI is set to the low power consumption mode. At this time, the RAM data is held and the registers are initialized. Battery backup mode is canceled by setting power-on reset to high.
10 clocks Power-on reset EXRS
PWRST 100ms or more Timer clocks CCKI, CCKO
Other clocks TCXO, XTCXO, CLKI, CLKO
Normal outputs TXD0 to 2, OTCXO, HOLDA
Fixed low
Tri-state outputs IODBK, RUN, CLKOUT Tri-state outputs ICS0, ICS1, IADR[18:1], IRD, IWR, DRD, DWR, XCS0
Fixed low
Hi-Z
Bidirectional (Input) SINT, IB[15:0], DCS0 to DCS5, DADR[15:0], DB[7:0], PORT[22:0] (Outut)
Fixed low Hi-Z
Inputs RXD0 to RXD2, IF0, HOLD, NMI, PMI
Fixed low
- 11 -
CXD2931R-9/GA-9
CXD2931R-9/GA-9 Initialization CXD2931R-9/GA-9 initialization is started by setting the reset input signal EXRS (Pin 27) to low level. The timing should satisfy the conditions noted below. 1. During power-on (power-on reset) (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
VDD Power supply, PWRST (Pin 28) 100ms or more VDD/2 EXRS (Pin 27)
VDD [V]
GND
The PWRST (Pin 28) signal should rise simultaneously with the power supply. The EXRS (Pin 27) signal should rise 100ms or more after the power supply and the PWRST signal have risen. Note that the PWRST signal should be left open during battery backup. 2. Initialization during operation (VDD = 3.0 to 3.6V, Topr = -40 to +85C)
Power supply, PWRST (Pin 28) VDD EXRS (Pin 27) 100s or more VDD/2
VDD [V]
GND
The internal registers can be initialized during operation by setting the EXRS (Pin 27) signal to low level for 100s or more. Keep the PWRST (Pin 28) signal at high level at this time.
- 12 -
CXD2931R-9/GA-9
* External Command Fetch Timing (XROMW = 0)
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (e) IRD (g) IB (16) (h) (f) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h) Address delay time
Item Read cycle time (Fex: @20MHz) Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time
Min. -- -- 2 2 0 0 11 0
Typ. 100 -- -- -- -- -- -- --
Max. -- 12 10 10 3 5 -- --
Unit ns ns ns ns ns ns ns ns
The load capacitance = 30pF.
* External Command Fetch Timing (XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD IB (16)
- 13 -
CXD2931R-9/GA-9
* External Data Access Timing (ICS0, ICS1/XROMW = 0) (1) Read (half-word access/XROMW = 0)
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (e) IRD (g) IB (16) (h) (f) (d)
(2) Write (half-word access/XROMW = 0)
CLKOUT (a) (b) IADR (c) ICS0, ICS1 (i) IWR (k) IB (16) (l) (j) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) Address delay time
Item Read/write cycle time (Fex: @20MHz) Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time Write signal fall delay time Write signal rise delay time Write data established time Write data hold time - 14 -
Min. -- -- 2 2 0 0 11 0 0 0 -- 5
Typ. 100 -- -- -- -- -- -- -- -- -- -- --
Max. -- 12 10 10 3 5 -- -- 1 2 5 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
The load capacitance = 30pF.
CXD2931R-9/GA-9
(3) Read (word access/XROMW = 0)
CLKOUT
IADR
ICS0, ICS1
IRD IB H (16) L (16)
(4) Write (word access/XROMW = 0)
CLKOUT
IADR
ICS0, ICS1
IWR IB L (16) H (16)
- 15 -
CXD2931R-9/GA-9
* External Data Access Timing (ICS0, ICS1/XROMW = 1) (1) Read (half-word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD IB (16)
(2) Write (half-word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IWR IB (16)
(3) Read (word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IRD IB H (16) L (16)
(4) Write (word access/XROMW = 1)
CLKOUT
IADR
ICS0, ICS1
IWR IB L (16) H (16)
- 16 -
CXD2931R-9/GA-9
* External Data Access Timing (XCS0, DCS0 to DCS5/no data wait) (1) Read (byte access/no data wait)
CLKOUT (a) (b) DADR (c) XCS0, DCS0 to DCS5 (e) DRD (g) DB (8) (h) (f) (d)
(2) Write (byte access/no data wait)
CLKOUT (a) (b) DADR (c) XCS0, DCS0 to DCS5 (i) DWR (k) DB (8) (l) (j) (d)
No. (a) (b) (c) (d) (e) (f) (g) (h) (i) (j) (k) (l) Address delay time
Item Read/write cycle time (Fex: @20MHz) Chip select fall delay time Chip select rise delay time Read signal fall delay time Read signal rise delay time Read data setup time Read data hold time Write signal fall delay time Write signal rise delay time Write data established time Write data hold time - 17 -
Min. -- -- 3 3 2 2 16 0 0 0 -- 5
Typ. 100 -- -- -- -- -- -- -- -- -- -- --
Max. -- 12 13 13 8 10 -- -- 2 3 12 --
Unit ns ns ns ns ns ns ns ns ns ns ns ns
The load capacitance = 30pF.
CXD2931R-9/GA-9
(3) Read (half-word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD DB H (8) H (8)
(4) Write (half-word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR DB L (8) H (8)
(5) Read (word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD DB HH (8) HL (8) LH (8) LL (8)
(6) Write (word access/no data wait)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR DB LL (8) LH (8) HL (8) HH (8)
- 18 -
CXD2931R-9/GA-9
* External Data Access Timing (XCS0, DCS0 to DCS5/data wait = 1) (1) Read (byte access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD DB (8)
(2) Write (byte access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR DB (8)
(3) Read (half-word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD DB H (8) L (8)
(4) Write (half-word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR DB L (8) H (8)
- 19 -
CXD2931R-9/GA-9
(5) Read (word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD DB HH (8) HL (8) LH (8) LL (8)
(6) Write (word access/data wait = 1)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR DB LL (8) LH (8) HL (8) HH (8)
* External Data Access Timing (XCS0, DCS0 to DCS5/data wait = 2) (1) Read (byte access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD DB (8)
(2) Write (byte access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR DB (8)
- 20 -
CXD2931R-9/GA-9
(3) Read (half-word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD DB H (8) L (8)
(4) Write (half-word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR DB L (8) H (8)
(5) Read (word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DRD DB HH (16) HL (16) LH (16) LL (16)
(6) Write (word access/data wait = 2)
CLKOUT
DADR
XCS0, DCS0 to DCS5
DWR DB LL (16) LH (16) HL (16) HH (16)
- 21 -
CXD2931R-9/GA-9
Application Notes The constants shown in the circuits below are the examples, and do not quarantee the circuit operation. 1. TCXO input (1) When inputting the binary-converted signal The TCXO (Pin 7) input signal should be 18.414MHz 3ppm.
Input
7
Open 8
(2) When performing the self-oscillation with the TCXO and XTCXO pins (Pins 7 and 8) The TCXO (Pin 7) input signal should be 18.414MHz 3ppm.
0.01F TCXO 1M 8 7
2. CPU clock generation Pin 32 is used to select that TCXO is used or that the self-oscillation is performed with the MCKI and MCKO pins (Pins 30 and 31). (1) TCXO solution (TCXO is used for CPU clock) Set Pin 32 to low. Pin 30: Low Pin 31: Open (2) When performing the self-oscillation with the MCKI and MCKO pins (Pins 30 and 31) Set Pin 32 to high. The crystal frequency should be less than 20MHz. The following circuit is just a reference, and is not guaranteed.
20pF 30 20MHz max. 20pF 10M 31
- 22 -
CXD2931R-9/GA-9
(3) Using internal clock Set PORT5 (Pin 131) to high. Connect the external parts as follows when performing the self-oscillation with the CCKI and CCKO pins (Pins 13 and 14).
220pF 13 32.768kHz 100ppm 220pF 10M 14
(4) Input IF signal
0.01F 18 1M 19
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CXD2931R-9/GA-9
Description of Application Circuit See the Application Circuit when using the CXD2931R-9/GA-9 to configure a GPS receiver. Points for caution are as follows. 1. Unused pins Software processing is performed to prevent undesired current from flowing to unused pins in the circuit diagram, so leave these pins open. 2. TCXO input The TCXO frequency is 18.414MHz 3ppm. Signals that have not been binary-converted should be input via a DC filter capacitor (C19 in the circuit diagram). Input binary-converted signals directly to Pin 7 (TCXO) without passing through C19 or R1 in the circuit diagram. Make sure the input level at this time satisfies the Electrical Characteristics. 3. IF input The CXD2931R-9/GA-9 interface is 1.023MHz, and does not accept other frequencies. Signals that have not been binary-converted should be input via a DC filter capacitor (C20). Input binary-converted signals directly to Pin 18 (IF0) without passing through C20 or R3 in the circuit diagram. Make sure the input level at this time satisfies the Electrical Characteristics. 4. TXD (SIO output) The TXD amplitude low level is 0.4V or less, and the high level is VDD - 0.4V (VDD = 3.0 to 3.6V) or more. When the LSI, etc., connected to TXD operates at 5V and has a CMOS input level, perform 3 to 5V conversion before inputting the signal. 5. Real-time clock The current software version uses an external real-time clock. Consult your Sony representative beforehand when using the internal real-time clock. When using an external real-time clock, connect Pin 13 (CCKI) to GND.
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Application Circuit
VSS VDD C1 0.1 47k 47k 47k 47k 47k 47k C2 0.1
VDD
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73
VSS
VDD
VSS
DB5
DB4
DB3
DB2
DB1
DB0
IB15
IB14
VDD
IB13
IB12
XCS0
DADR9
DADR8
DADR7
DADR6
DADR5
DADR4
DADR3
DADR2
DADR1
DADR15
DADR14
DADR13
DADR12
DADR11
47k 111 SINT/PORT22 112 DCS0/PORT21 113 VDD C3 0.1 114 DCS1/PORT20 115 DCS2/PORT19 116 DCS3/PORT18 117 DCS4/PORT17 118 DCS5/PORT16 119 PORT15 120 PORT14 121 VSS 122 PORT13 123 PORT12 124 PORT11 125 PORT10 126 PORT9 127 PORT8 128 PORT7 129 VDD IC1 CXD2931R-9/GA-9
109 DB6 110 DB7
DADR10
DADR0
47k
DWR
DRD
IB11
IB10
IB9
IB8 72 IB7 71 VSS 70 IB6 69 IB5 68 IB4 67 IB3 66 IB2 65 IB1 64 VDD 63 IB0 62 C4 0.1
Recommended components IC1: CXD2931R-9/GA-9 IC2: Real-time clock Made by RICOH (RS5C313) IC3: Voltage regulator (for step-down transformation) Made by SEIKO INSTRUMENTS (S81218SG, steps down 3V to 1.8V) TCXO: Made by Tokyo Denpa Oscillator frequency: 18.414MHz 3ppm
Note) Set PORT5 to low when using an external timer, and set PORT5 to high when using an internal timer.
IADR18 61 IADR17 60 IADR16 59 IADR15 58 IADR14 57 IADR13 56 VSS 55 IADR12 54 IADR11 53 IADR10 52 IADR9 51 IADR8 50 IADR7 49 IADR6 48 VDD 47 IADR5 46 IADR4 45 IADR3 44 IADR2 43 IADR1 42 XROMW 41 ICS1 40 VSS 39 ICS0 38 IRD 37 C7 0.1
NC
NC
VOUT
VIN
GND
CLKO
CLKS
CLKOUT
AVD
AVIN
VRT
VRB
AVS
VSS
TCXO
XTCXO
VDD
OTCXO
TEST0
TEST1
CCKI
CCKO
VSS
ICST0
ICST1
IF0
IF0O
TCXOS
VDD
HOLD
NMI
PMI
HOLDA
IODBK
EXRS
PWRST
VSS
CLKI
VDD
RUN
C10 0.1 1
3.6V
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
TXD
2 R1 1M R3 1M VDD C14 0.1 C19 0.01 C15 C16 220p 220p When using the internal timer C20 0.01 C17 0.1 C18 0.1 VSS
RXD
3
VDD
VSS
VSS
VDD
VSS
VDD
TCXO (18.414MHz)
4
IF (1.023MHz) C13 0.1
5
VDD
D2 RB400D-T146
R2 10M X2 32.768k
RESET
6
GND
7
VSS
TCXO
C11 3.3
IF RESET
Input 3.6V in consideration of voltage step-down by diode (D2).
CXD2931R-9/GA-9
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
IWR
- 25 -
When using an external timer 130 PORT6 131 PORT5 132 PORT4 133 PORT3 134 PORT2 135 PORT1 136 PORT0 137 VSS 138 TXD2 139 RXD2 140 TXD1 141 RXD1 142 TXD0 143 RXD0 144 VDD IC2 RS5C313 INT VSS 4 OSCO SIO 3 OSCI SCL 2 VDD CE 1 C5 0.1 X1 5 32.768k C6 6 10p 7 C9 8 10p
IC3 5812185G
5
4
3
2
1
D1 RB400D-T146
BT1 3.0V
TXD0
RXD0
CN1
VSS
CXD2931R-9/GA-9
Package Outline CXD2931R-9
Unit: mm
144PIN LQFP (PLASTIC)
22.0 0.2 20.0 0.1 108 109 73 1.7 MAX 1.4 0.1
72
B
A 144 37
1
0.5
36 b 0.08 M S S 0.1 0.05
0.1
S
(21.0)
0 to 10 DETAIL A
0.5 0.15
DETAIL B
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-144P-L01 LQFP144-P-2020 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 1.3 g
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0.125 0.04
b = 0.20 0.03
CXD2931R-9/GA-9
Package Outline CXD2931GA-9
Unit: mm
144PIN LFLGA
0.2 SA 13.0
1.4MAX 0.01
PIN 1 INDEX
13.0
x4 0.15 S 3 - 0.50 0.55 R P N M L K J H G F E D C B A 1 2 3 4 5 6 7 8 9 101 112131415 0.5 0.55 0.8 0.9 A 144 - 0.40 0.05 0.08 M S A B
0.2
0.20 S
SB
DETAIL X
0.55
B
0.55 0.5
0.9
0.8
PACKAGE STRUCTURE
PACKAGE MATERIAL ORGANIC SUBSTRATE NICKEL & GOLD PLATING COPPER 0.5g
SONY CODE EIAJ CODE JEDEC CODE
LFLGA-144P-01 P-LFLGA144-13x13-0.8
TERMINAL TREATMENT TERMINAL MATERIAL PACKAGE MASS
0.10 S
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X
Sony Corporation

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